1. Field of the Invention
The present invention relates to a data processing system containing a scalar unit and a vector unit, wherein a serializing operation is performed, using a post instruction and wait instruction between one or more vector instructions and a scalar instruction.
In a data processing system containing a scalar unit and a vector unit wherein the scalar unit carries out scalar instructions and the vector unit carries out vector instructions, execution of a plurality of vector instructions and scalar instructions are carried out in parallel, and prefetching of instructions and data is carried out. In the above data processing system, the order of operations to access the storage must be ensured between vector instructions and between a vector instruction and a scalar instruction, although the order of operations to access the storage is ensured by nature between scalar instructions in the scalar unit. The serializing operation is carried out to ensure the order of the operations to access the storage between vector instructions and between a vector instruction and a scalar instruction.
2. Description of the Related Art
FIG. 1 shows a data processing system containing a scalar unit and a vector unit. In FIG. 1, the scalar unit 1' fetches instructions in a program in order, executes the fetched instruction when the instruction is a scalar instruction, or sends the fetched instruction to the vector unit 2' when the instruction is a vector instruction to make the vector unit execute the instruction. In the vector unit 2', the vector instruction control circuit 12' in the vector control unit 11 receives the vector instruction which is transferred from the scalar unit 1', and controls the execution of the vector instruction. When the vector instruction is a load instruction or a store instruction, the execution of the instruction is controlled in the vector load/store control circuit 13, and an operation to access the main storage 10 is carried out through the memory control unit 14'. A load operation of vector data which is read from the main storage 10 in the vector register 7 or a store operation of vector data which is read from the vector register 7 in the main storage 10 is carried out in the load/store pipeline 8 or 9 under the control of the vector load/store control circuit 13. An operation to access the main storage 10 from the scalar unit 1' is also carried out through the main storage unit 14'.
It is desired that the scalar unit and the vector unit operate in parallel as long as it is possible. However, when data which is fetched for an execution of a vector instruction or a scalar instruction is obtained by an execution of a preceding vector instruction or a scalar instruction, the order of operations to access the main storage 10 must be ensured between the preceding instruction and the following instruction. Since requests for accessing the main storage can arise in parallel in the scalar unit and the plurality of load/store pipelines, the above ensuring of the order must be performed between a preceding vector load instruction and a following vector instruction, between a preceding vector store instruction and a following vector instruction, between a preceding scalar store instruction and a following vector instruction, between a preceding vector load instruction and a following scalar instruction, and between a preceding vector store instruction and a following scalar instruction. The order of operations to access the main storage between a preceding scalar load instruction and a following vector instruction is ensured by nature. The order of operations to access the storage is ensured by nature between scalar instructions in the scalar unit because the scalar unit contains one pipeline.
Generally, the order of operations to access the main storage between a preceding vector load instruction and a following vector instruction, between a preceding vector store instruction and a following vector instruction, between a preceding scalar store instruction and a following vector instruction, and between a preceding vector load instruction and a following scalar instruction, are respectively ensured simply regarding the order of obtaining a right of access to the main storage.
On the other hand, the order of operations to access the main storage between a preceding vector store instruction and a following scalar instruction, is ensured considering the following situation. The scalar unit usually contains a buffer memory (cache) for temporarily storing portions (blocks) of data of the main storage to which portions (blocks) the scalar unit has recently accessed. When the address of the main storage to which address a result of an execution of a vector store instruction is stored, corresponds to one of the blocks of data which is temporarily stored in the buffer memory, the corresponding block of data in the buffer memory must be invalidated before data fetch operations for following scalar instructions are carried out to the buffer memory. Therefore, an execution of a scalar instruction which includes a data fetch operation, must be stopped until the above invalidation of the buffer memory is completed.
To ensure the above order, conventionally, a serializing operation using a post instruction and a wait instruction is carried out. In the serializing operation, control is performed so that an operation for accessing the main storage for an instruction preceding the post instruction, is carried out before an operation for accessing the main storage for an instruction following the wait instruction. In this operation, no control is performed for the instructions between the post instruction and the wait instruction, regarding the order of operations to access the main storage.
FIG. 2 shows an example of a sequence of instructions which includes a post instruction and a wait instruction for carrying out a serializing operation. In FIG. 2, VSTi (i=1 to 8) each denote a vector store instruction, POST denotes a post instruction, WAIT denotes a wait instruction, and LD denotes a scalar load instruction. The execution of the scalar load instruction LD which follows the wait instruction, is suspended until a right to access the main storage for the execution of the vector store instruction VST1 which precedes the post instruction POST is obtained.
FIG. 3 shows a conventional flow of executions of the vector store instructions VST1 to VST8 of FIG. 2. Two vector store instructions are executed simultaneously in parallel in the two load/store pipelines 8 and 9 of FIG. 1. In FIG. 3, the parallelogram for each vector store instruction indicates a plurality of processing flows which are processed in a load/store pipeline. In the conventional serializing operation, an active post pending signal POST-PENDING which indicates whether or not the executions of the vector instructions preceding a post instruction is completed yet, is output from the vector unit to the scalar unit, the post pending signal POST-PENDING is made active when the execution of the post pending signal POST-PENDING is started in the vector unit, and is made inactive when the executions for all vector instructions preceding the post instruction are completed. In addition, when an execution of a wait instruction is started in the vector unit, a wait acknowledge signal WAIT-ACK is output from the vector unit to the scalar unit. In the scalar unit, when a wait instruction is detected, execution of scalar instructions following the wait instruction is first stopped, and the scalar unit awaits the above wait acknowledge signal WAIT-ACK. Then, when the scalar unit receives the wait acknowledge signal WAIT-ACK, the scalar unit determines whether or not the executions for all vector instructions preceding the post instruction are completed, based on the received post pending signal POST-PENDING. When the post pending signal POST-PENDING is inactive, the scalar unit releases the execution of the scalar instructions following the wait instruction, e.g., a scalar load instruction LD shown in FIG. 2 can be executed. Namely, conventionally the judgment for the release of scalar instructions following a wait instruction can be made after the wait instruction is started in the vector unit.
However, in the above conventional serializing operation, there is a delay between the time of the change of the post pending signal POST-PENDING to inactive, and the output time of the wait acknowledge, as shown in FIG. 3, i.e., the scalar unit cannot immediately detect the change of the post pending signal POST-PENDING from active to inactive. Therefore, in the prior art, the start of the execution of the scalar instructions following the wait instruction, and accordingly execution of all the instructions following the wait instruction, is delayed according to the above delay between the time of the change of the post pending signal POST-PENDING to inactive, and the output time of the wait acknowledge. The reason why the above judgment for the release of scalar instructions following a wait instruction is made at the timing of the reception of the wait acknowledge signal, is that, conventionally, the scalar unit cannot recognize when a post instruction preceding the wait instruction is started in the vector unit, i.e., when the post pending signal POST-PENDING becomes active.